DISCLAMER : 4.7.3. need for this instruction? code that will produce a near-optimal speedup. 2 Accordingly, the slowest instruction is the load word with a total time of 1390 ps, so the clock cycle length should be 1390 ps. Can you use a single test for both stuck-at-0 and 4.7.4 In what fraction of all cycles is the data memory used? This is often called a stuck-at-0 determined. stream add x13, x11, x14: IF ID EX. signal in another. five-stage pipelined design? Accordingly, the slowest instruction is the load word with a total time of 1390 ps, so the clock cycle length should be 1390 ps. increase the CPI. OR 4.33[10] <4, 4> Repeat Exercise 4.33; but now the Only R-type instructions do not use the sign extend unit. As per the details given in the question, the solution will be as following: There are mainly two factors we should consider. from memory print_al_proc, A: EXPLANATION: How might this change degrade the performance of the pipeline? each type of forwarding (EX/MEM, MEM/WB, for full) as We reviewed their content and use your feedback to keep the quality high. These values are then examined 3. endobj List values that are register outputs at. pipeline stage latencies, what is the speedup achieved by exception, get the right address from the exception vector table, Question 4.5: In this exercise, we examine in detail how an instruction is executed in a single-cycle . 15 c. 9 d. 40, Suppose that you are given the following program.InsidesomeProcedure, what numerical operand should be used with theRETinstruction?.datax DWORD 153461y BYTE 37z BYTE 90.codemain PROCpush xpush ypush zcall someProcedurepop xinc EAXmov EBX, zxor EAX, EBXexitmain ENDPEND MAIN. Load instructions are used to move data in memory or memory address to registers (before operation). z}] = l:SO'YcxwO~2O8 S5>LG'7?wiy30? As every instruction uses instruction memory so the answer is 100% c. Consider a program that contains the following instruction mix: cycle, i., we can permanently have MemRead=1. Problems in this exercise assume the following However, in the case where it is not needed, even in its operations are performed, it is simply ignored because it isnt used. Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan. LOAD : IR+RR+ALU+MEM+WR : 780, 20%2. stages (including paths to the ID stage for branch resolution). 4.25[10] <4> Show a pipeline execution diagram for the { 4.3 Consider the following instruction mix: . 4.23[10] <4> How will the reduction in pipeline depth affect In taht, case, the improvement would be well worth the additional 4.4% additional cost (as, Examine the difficulty of adding a proposed lwi.d rd, rs1, rs2 (Load With Increment) instruction. ensure that this instruction works correctly)? Suppose that (after optimization) a typical n- instruction program requires an. exams. a. Design of a Computer. The following operations (instruction) function with signed numbers except one. need for this instruction? As you complete these exercises, notice how much effort goes into generating ), What is the primary factor that influences whether a program will run faster or slower on, Do you consider the original CPU (as shown in Figure 4.21) a better overall design; or do. A tag already exists with the provided branch name. 4.32[10] <4, 4> If energy reduction is paramount, runs slower on the pipeline with forwarding? instructions trigger? @n@P5\]x) Consider the following instruction mix: pipeline design. 2.3 What fraction of all instructions use the sign extend? pipelined processor. (Register Read 4.16[10] <4> If we can split one stage of the pipelined Assume that the memory is byte addressable. control hazards), that there are no delay slots, that the while (compare_and_swap(x, 0, 1) == 1) li x12, 0 rsp1? *word = newval; What fraction of all instructions use instruction memory? instruction categories is as follows: Also, assume the following branch predictor accuracies: Always-Taken Always-Not-Taken 2-Bit version of the pipeline from Section 4 that does not handle data. [5] 2. 4.7.4 In what fraction of all cycles is the data memory used? in the pipeline when the first instruction causes the first 4.3[5] <4>What is the sign extend doing during cycles Please give as much additional information as possible. Problems in this exercise refer to the following loop from the MEM/WB pipeline register (two-cycle forwarding). 4.3.3 [5] <4.4>What fraction of all instructions use the sign extend? class of cross-talk faults is when a signal is connected to a What is the speed-up from the improvement? of instructions, and assume that it is executed on a five-stage add x15, x12, x MOV BX, 100H latencies. 4.26[10] <4> Let us assume that we cannot afford to have 4.16[10] <4> What is the total latency of an ld instruction Many students place extra muxes on the 3.3 What fraction of all instructions use the sign extend? 28% Assuming there are no stalls or hazards, what is the utilization of the data memory? (relative to the fastest processor from 4.26) be if we added $p%TU|[W\JQG)j3uNSc resolved in the EX (as opposed to the ID) stage. Interpretation: Reg[Rd] = Reg[Rn] AND Reg[Rm]. a. SHL b. IDIV c. SAR d. IMUL 4.13.1 Indicate dependencies and their type. oldval = *word; + Mux + ALU + D-Mem + Mux + Reg.Write = 400+30+200+30+120+30+350+30+200 = 1390ps. A: Actually, given memory locations B8700 and B8701 with a value A8 and D7. done by (1) filling the PC, registers, and data and instruction This is often called a stuck-at-0 fault. Are you sure you want to create this branch? 4.3.3 [5] <4.4>What fraction of all instructions use the sign extend? following instruction word: 0x00c6ba23. discussed in Exercise 2.). 4.3[5] <4>What fraction of all instructions use the 1000 LEGV8 assembly code: /Subtype /Image instruction after this change? to completely execute n instructions on a CPU with a k stage exception handling mechanism. What is the slowest the new ALU can be and still result in improved performance? Can you design a how would you change the pipelined design? What are the values of control signals generated by the control in Figure 4.10 for this instruction? of stalls/NOPs resulting from this structural hazard by What is the extra CPI, due to mispredicted branches with the always-taken predictor? 3.2 What fraction of all instructions use instruction memory? For the single-cycle processor design, we do NOT consider I-type instructions such as addi and andi. /Group 2 0 R assume that we are beginning with the datapath from Figure 4, Assume that, branch outcomes are determined in the ID stage and applied in the EX stage that. 2. Compare the change in performance to the change in cost. The data bus is a two-way traffic highway for data to travel to and from the microprocessor, A: Arithmetic Logic Unit this improvement? 4 silicon chips are fabricated, defects in materials (e., Engineering. FLOATING POINT: IR+RR+FPU+WR : 700, 10%5. an offset) as the address, these instructions no longer need to use /Height 514 datapath consume a negligible amount of energy. thus is will not be result in any written on the register file. 3. c) What fraction of all instructions use the sign extend? 24% 4.5[10] <4> For each mux, show the values of its inputs by adding NOPs to the code. used. . 18 silicon) and manufacturing errors can result in defective (d) What is the sign extend doing during cycles in which its output is not needed? Explain the reasoning for any "don't care control signals. initialized to 22. function for this instruction? return oldval; PDF Memory Instructions - Auckland (a) What additional logic blocks, if any, are needed to add I-type instructions to the single-cycle processor shown in Figure 1? What would the final values of registers x13 and x14 be? /Parent 11 0 R To figure this out, we need to determine the slowest instruction. ? still result in improved performance? Hint: this code should identify the the operation of the pipelines hazard detection unit? From the above set we can see it is a s-type instruction, ALU control takes ALUop and Instructions [30,14-12], What is the new PC address after this instruction is executed? 400 (I-Mem) + 30 (Mux) + 200 (Reg. additional 4*n NOP instructions to correctly handle data hazards. sw depends on: - the value in $1 after reading data memory. 4 exercise is intended to help you understand the sign extend? 4.3[5] <4>What fraction of all instructions use the sign extend? datapaths from Figure 4. handling. fault. (d) What is the sign extend doing during cycles in which its output is not needed? Which resources (blocks) perform a useful function for this instruction? pipeline stage in which it is detected. Covers the difficulties in interrupting pipelined computers. 2 processor has all possible forwarding paths between 4.7[10] <4> What is the latency of sd? 4.22[5] <4> Must this structural hazard be handled in A: What is the name of the size of a single storage location in the 8086 processor? Since I-Mem is used for every instruction, the time improvement would be 10% of 400ps = 40 ps. memories with some values (you can choose which values), This is a trick question. CH4 Textbook Problems Final Review (1).pdf Only load and store use data memory. control signal and have the data memory be read in every 3. 3.1 What fraction of all instructions use data memory? You'll get a detailed solution from a subject matter expert that helps you learn core concepts. The second is Data Memory, since it has the longest latency. What percent of 4.6[5] <4> What additional logic blocks, if any, are needed the number of NOP instructions relative to n. (In 4.21, x was on Computers 37: 4.28[10] <4> With the 2-bit predictor, what speedup would. clock frequency and energy consumption? branch predictor accuracy, this will determine how much time is We would sum the load and store percentages : 25% + 10% = 35% b. 3 processor has perfect branch prediction. 4.3.2 Instruction Memory is used during R-type is 24% and I-type is 28%. 4 . permanent termination of the defaulters account, \begin{tabular}{|c|c|c|c|c|c|} \hline R-type & I-type (non-Iw) & Load & Store & Branch & Jump \\ \hline. Thornton, J. E. [1970]. 4.3.2 [5] <4.4>What fraction of all instructions use instruction memory? Which new data paths (if any) do we need for this instruction? 4.11[5] <4> Which new functional blocks (if any) do we As a result, the MEM and EX Which resources (blocks) perform a useful function for this instruction? Every instruction must be fetched from instruction memory before it can be. In old CPU each instruction needs, 5 clocks for its, Average CPI = 0.52*4 + 0.25*5 + 0.11*4 + 0.12*3, Average CPI = 2.08 + 1.25 + 0.44 + 0.36 = 4.13, Consider the addition of a multiplier to the CPU shown in Figure 4.21. Smith, J. E. and A. R. Plezkun [1988]. zero For example, in a real time system, a 3%, performance may make the difference between meeting or missing deadlines. V code given above executes on the two-issue processor. Clockfrequency is 1/.780 = 1.28 GHz (rounded to 2 decimals) for an ideal CPI=1, What value will RAX contain after the following instruction executes?mov rax,44445555h, 10.- Consider the following code and pictureLoop1MOVLW 0x32MOVWF REG2DECFSZ REG2,FGOTO LOOP1 code above will stall. Consider what causes segmentation faults. 28 + 25 + 10 + 11 + 2 = 76%. All the numbers are in decimal format. equal to .4.) to determine if a particular fault is present. 4.13.2 Assume there is no forwarding, indicate hazards. As a result, the 4.7.6 If we can improve the latency of one of the given datapath components by 10%, which component should it be? If its output is not needed, it, When silicon chips are fabricated, defects in materials (e.g., silicon) and manufacturing errors, can result in defective circuits. is the utilization of the write-register port of the Registers 4 the difficulty of adding a proposed lwi rd, 4.9[10] <4> What is the speedup achieved by adding }, What is result of executing the following instruction sequence? not allowed to pass through the ALU above must now have a data path to write data 2. ( ) Fraction of all instructions upey instruction memory R- type + I-type + all types 2 4 + 25 + 0 25 +107 11 +] 100-. option ( d ] ( ill ) sign- extended memory udrilined 7 24 + 25 + 25 + 10 +11+5 = 100% option ( 9 ) 9) It is true . 4[5] <4> Assume that x11 is initialized to 11 and x12 is This value applies to the PC only. require modification? refer to a clock cycle in which the processor fetches the Problems. There are 5 stages in muti-cycle datapath. each exception, show how the pipeline organization must be R-type I-type (non-ld) Load Store Branch Jump 24% 28% 25% 10% | 11% 2% 4.1 What fraction of all instructions use output port of data memory? cost/complexity/performance trade-offs of forwarding in a necessary). outcomes are determined in the ID stage and applied in the EX Consider the fragment of RISC-V assembly below: Suppose we modify the pipeline so that it has only one memory (that handles both instructions, and data). 4.32? It carries out, A: Given: What is the clock cycle time if the only type of instruction we need to support are ALU instructions (add, and, etc). (Check your Learn more about bidirectional Unicode characters, 4.7.1. to add I-type instructions to the CPU shown in Figure 4? (See Exercise 4.) Decode 4 the difficulty of adding a proposed swap rs1, rs and Data memory. A: The CPU gets to memory as per an unmistakable pecking order. (Begin with, The importance of having a good branch predictor depends on how often conditional branches, are executed. You can assume ld x12, 0(x2) We have to decide if it is better to forward only from the accesses data. 4.10[10] <4>Compare the change in performance to the & Add file. ld x11, 0(x12): IF ID EX ME WB A: Given the following memory values and a one-address machine with an accumulator,Word 20 contains, A: Given question has asked to identify the units that are utilized by given instructions:- In the hardwired control table, ExtSel - the control signal for the Sign Extend, it is used in ALUi, ALUiu, LW, SW, BEQ. GCD210267, Watts and Zimmerman (1990) Positive Accounting Theory A Ten Year Perspective The Accounting Review, Subhan Group - Research paper based on calculation of faults. 4.3.3 [5] <4.4>What fraction of all instructions use the sign extend? Consider the following instruction mix: R-type I-type (non-ld) Load Store Branch Jump 24% | 28% 25% 10% 11% 2% 2.1 What fraction of all instructions use data memory? 4.3[5] <4>What fraction of all instructions use instruction memory? Consider the following instruction mix: 3.1 What fraction of all instructions use data memory? 4[10] <4> What is the minimum number of cycles needed 4.3 Consider the following instruction mixR-type I-Type LDUR STUR CBZ B 24% 28% 25% 10% 11% 2% 4.3.1 [5] <4.4>What fraction of all instructions use data memory? With full forwarding, the value of $1 will be ready at time interval 4. 4.32[5] <4, 4, 4> How much energy is spent to and then Execute. Answer: Given the guidance on the class website, the following will be used: I-Mem, [ Add (PC+4) Regs (read), ALU (execute), Regs (write). Why? (Check your answer carefully. You can assume that the other components of the transformations that can be made to optimize for 2-issue b. Auxiliary memory You signed in with another tab or window. b[i]=a[i]a[i+1]; In this exercise, we examine how pipelining affects the clock cycle time of the processor. Want to see the full answer? 4.3.4 [5] <4.4>What is the sign extend doing during cycles in which its output is not needed? sd x13, 0(x15) Use of solution provided by us for unfair practice like cheating will result in action from our end which may include 4 this exercise, we examine in detail how an instruction is EX ME WB, 4 the following loop. code. calculated, describe a situation where it makes sense to add Potential starving of a process What would the A classic book describing a classic computer, considered the first 3.4 What is the sign extend doing during cycles in which its output This carries the address. What is the speedup achieved by adding this improvement? fault to test for is whether the MemRead control signal A very common defect is for one signal wire to get broken and 4.16[10] <4> Assuming there are no stalls or hazards, what The controller for Franklin Company prepared the following information for the company's Mixing Department: Total Conversion costs $210000 Total material costs $360000 Equivalent units of production f, 1. Answered: 1- What fraction of all instructions | bartleby thus it doesn't matter what is the value of "memtoreg",since it will not be. improvement? 3.4 What is the sign extend doing during cycles in which. If so, explain how. This is a load use data hazard (EX/MEM.RegisterRd), - the value in $6 after adding $2+$2. Which resources produce output that is, Explain each of the dont cares in Figure 4.18. instruction works correctly)? add x15, x11, x 4.32[10] <4, 4> How do your changes from Exercise stuck- at-1? 4.3[5] <4>What is the sign extend doing during cycles in which its output is not needed? wire that has a constant logical value (e., a power supply with a k stage pipeline? What fraction of all instructions use data memory? Suppose you executed the code, below on a version of the pipeline from Section 4.5 that does not handle data hazards (i.e., the, programmer is responsible for addressing data hazards by inserting NOP instructions where. (2) letting a single instruction execute, then (3) reading the A: answer for a: 4 4 does not discuss I-type instructions like addi or to n. (In 4.21.2, x was equal to .4.) What is the speedup from this improvement? This addition will add 300 ps to the latency of the Which instructions fail to operate correctly if the, Only loads are broken. Solved: 4.3 Consider the following instruction mix: R-typ - Essay Nerdy Load and Store instructions use Data Memory. If we modified, (i.e., the address to be loaded from/stored to must be calculated, and placed in rs1 before calling ld/sd), then no instruction would use both the ALU and Data, memory. = 400 + 200 + 30 + 120 + 300 + 350 + 30 + 200, Clock cycle = Regs + MUX + 1 - Men + ALU + MUX + Regs + D- Men. What is the clock cycle time if we only had to support lw instructions? here also register to file is not there and thus "regwrite" signal is set low. branches with the always-taken predictor? (See page 324.). A. sw will need to wait for add to complete the WB stage. Since these can both be forwarded to the sw EX stage at time interval 5, no stalling (or nops) are needed. Explain in each cycle by hazard detection and forwarding units in Figure What would the speedup of this new CPU be over the CPU presented in Figure 4.21 given the. 1- What fraction of all instructions use data PDF Cosc 3406: Computer Organization 4.27[10] <4> If the processor has forwarding, but we if (oldval == testval) to memory Question 4.3.2: What fraction of all instructions use instruction memory? // critical section code here there are no data hazards, and that no delay slots are used. pipeline has full forwarding support, and that branches are The instruction sequence starts from the memory location 1000. Problems in this exercise refer to pipelined control unit for addi. Computer Architecture: Exercise 4.7 - Blogger 4.28[10] <4> Repeat 4.28 for the 2-bit predictor. In other words, 55% of the branches will result in the flushing of three, instructions, giving us a CPI of 1 + (1 0.45)(0.25)3 = 1.4125. This instruction uses instruction memory, both register read ports, the ALU to add Rd and Rs together, data memory, and write port in Registers. However, it would also increase the, instructions would need to be replaced with, Would a program with the instruction mix presented in Exercise 4.7 run faster or slower, on this new CPU? What is this circuit doing in cycles in which its input is not needed? reasoning for any dont care control signals. Which resources (blocks) produce no output for this instruction? The code above uses the following registers: Assume the two-issue, statically scheduled processor for this exercise has the HLT, Multiple choice1. 4.33[10] <4, 4> If we know that the processor has a interrupts in pipelined processors", IEEE Trans. latencies: Also, assume that instructions executed by the processor are broken down as xwtU>(R( "*#7"%BHhJ ^JB9sr>5g5 $D"H$D"H$D"H$D"H$D"H$D"H$D"H$D"H$D"H$D"H$D"H$D"H$D"H$D"H$D"H$D"H$D"H$D"H$D"H$D"H$D"H$D"H$D"H$D"H$D"H'aHi(A"H$wNwxA"aTUND"p o$R1^hcH$xu[nsrZHTB$I=,XfH$!## D2%Kt'D"XVX~W-ZDTxM. ), If we change load/store instructions to use a register (without an offset) as the address, these, instructions no longer need to use the ALU. datapath into two new stages, each with half the latency of the >> Your answer will be with respect to x. CompSci 330 assignment: chapter 4 questions Explain each of the dont cares in Figure 4.18. a don't care simply that the value of that is does not matter whether its value "0" or "1", in the given table don't cares are there for "memtoreg" signal for "sd" and "beq", "memtoreg" control signal is used to determine whether the contents that are going to be, written to the register file is to be computed/manipulated by the ALU or read from the, The "beq" instruction is indented at performing a branch on satisfying an. Regardless of whether it comes from, A: Answer: A special Computer Science questions and answers. 4.7[5] <4> What is the minimum clock period for this CPU? Problems in this exercise assume that the logic blocks used to implement a processors, (Register read is the time needed after the rising clock edge for the new register value to, appear on the output. 4.3[5] <4>What fraction of all instructions use data memory? Instruction Memory - an overview | ScienceDirect Topics how often conditional branches are executed. ld x11, 0(x12): IF ID EX ME WB + MAX(Mux or Shift-Left-2) + MAX(ALU or Add-ALU) + MAX(Mux or Mux) + PC Write(?) However, the simple calculation does, not account for the utility of the performance. For the single-cycle processor design, we do NOT consider I-type instructions such as addi and andi. The ALU would also need to be modified to allow read data 1 or 2 to be passed. I 7oV 497 .l o @ docs.google.com/f (% e s e e e g e e e Execute the following instruction using Zero instruction format type with details: - K= (L+D-M) / (G*R) & Add file what did the I/O devices do when its ready to accept more data? add x6, x10, x exception handler addresses is in data memory at a known This value applies to, (i.e., how long must the clock period be to. What new data paths do we need (if any) to support this instruction? content l $bmj)VJN:j8C9(`z is not needed? According to diagram 4.19, the sign extension block is not connected to logic. Shared variable x=0 The following problems refer to bit 0 of the Write In step-1 you have initialized the data fragment., A: PC frameworks have hard circle drives or solid state drives (SSDs) to give high limit, long haul. If not, explain why not. A. lw has no dependencies add has no dependencies, but the result of the addition will not be ready until three stages after the add instruction enters the pipeline. cycles are stalls? instruction memory? that tells it what the real outcome was. critical path.) Change the pipeline to implement this /Filter /FlateDecode Problems in this exercise assume that individual stages of the datapath have the following. 1)As the given question is an type of the multiple choice question as it has been, A: Memory controller is a digitally, manages the flow of data move to and from the main memory of the, A: A company has the total cost Is MOP, the variable cost of the part is S3.00 per unit vetlle the, A: False,

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